1. Field of the Invention
The present invention relates to the field of liquid crystal display device, and in particular to a drive circuit of liquid crystal panel.
2. The Related Arts
The progress of science and technology and the improvement of living quality of human beings makes liquid crystal display devices widely used everywhere in daily living. People are now asking for more for the liquid crystal display devices and start demanding large display screen and fast response. However, increasing the size of the liquid crystal panel brings more complicated wire lay-out. Also, precise control pixel electrodes are getting more difficult due to wiring delay caused by the increase of number of pixel electrodes driven by a TFT (Thin-Film Transistor) substrate and feedback caused by the existence of TFT parasitic capacitor.
FIG. 1 is a schematic view showing the structure of a basic drive circuit of TFT array substrate. In the drawing, pixel electrodes are shown distributed in the entire TFT substrate and each pixel electrode is connected to a drain terminal D of at least one TFT. The source terminal S of each TFT is connected to at least one data line and a plurality data lines collectively constitutes a data bus structure. The gate terminal G of each TFT is connected to at least one gate line and a plurality of gate lines collectively constitutes a gate bus structure. The data bus structure and the gate bus structure collectively control data writing of the pixel electrode. In the substrate shown in the drawing, the pixel electrode P(i,j) of the ith column and jth row is commonly controlled by the gate line G(j) and data line S(i). When a writing operation is performed on the pixel electrode, the gate line G(j) is set at a high level to set the thin-film transistor T(I,j) in a conducting state. Under this condition, the magnitude of the drive voltage applied through the data line S(i) causes the liquid crystal molecules neighboring a site opposing the pixel electrode P(I,j) to rotate according to predetermined rotation direction so as to achieve displaying of image. Such a writing operation is performed in row-wise manner, so that when the gate line G(j) is in the high level, all the pixel electrodes of the jth row can perform a writing operation.
However, with the increase of the numbers of rows and columns of the pixel electrodes distributed in a matrix form on a TFT substrate, the lengthened gate lines and data lines cause time delay in the drive circuit. On the other hand, the parasitic capacitor Cgd existing between the gate terminal G and the drain terminal D of a thin-film transistor affects the gate voltage Vg controlling conduction and cutoff of the thin-film transistor, especially for the neighboring site of the pixel electrode P(n,j) that is located at a distal end away from the data bus circuit, where due to the influence of negative feedback voltage caused by the parasitic capacitors Cgd of the previous (n−1) thin-film transistors that the gate signal passed first and circuit delay, this site may have an extended response time and also suffers decay of gate voltage caused by the negative feedback, possibly making the thin-film transistor T(n,j) not conducting on, or not conducting on or not completely conducting on within a fixed time period when a source drive voltage Vs(n,j) is applied to drive the liquid crystal molecules to rotate. This makes the liquid crystal molecules of the pixel electrode not rotating or not rotating in the predetermined direction, thereby causing change of transmittance and variation of contrast around the site and thus affecting the quality of displaying.
FIG. 2 is a schematic view showing connection of drive circuit of each pixel electrode, wherein the ith data line S(i) is connected to the source terminal S of the thin-film transistor T(i,j) at the ith column and jth row. The jth gate line G(j) is connected to the gate terminal G of the thin-film transistor T(i,j) at the ith column and jth row. The drain terminal D of the thin-film transistor T(i,j) at the ith column and jth row is connected to the pixel electrode P(I,j) at the ith column and jth row. The symbol Cgd indicates the parasitic capacitor between the gate terminal G and the drain terminal D. The parasitic capacitor Cgd is inherent to the characteristics of the thin-film transistors. The symbol Cic indicates a liquid crystal capacitor between the TFT substrate and a CF substrate, Cs is a compensation capacitor between the TFT substrate and Vcom terminal and the compensation capacitor is provided for compensating for voltage drop of Cic through electrical discharging in order to properly extend the retention time for direction change of liquid crystal molecules in the area of Cic.
FIG. 3 shows waveform of drive voltage for the thin-film transistor shown in FIG. 1, wherein VG(j) is an idea waveform on the jth row supplied by the gate bus, Vg(N,j) is the waveform that has passed through the parasitic capacitors Cgd of the previous (N−1) thin-film transistors and circuit delay, and Vgh and Vgi are respectively high voltage and low voltage of Vg (N,j). When voltage is greater than the conduction threshold voltage VT of the thin-film transistor, the thin-film transistor is conducted on and the drive voltage Vg(N,j) on the data line S(N) performs a writing operation on the pixel electrode by driving the liquid crystal molecules neighboring the pixel electrode to rotate. When the gate voltage Vg(N,j) is greater than the conduction voltage of the thin-film transistor, charging is effected on Cic, Cs, Cgd through the rising edge of Vg (N,j) to achieve charging saturation and discharging in reverse direction is effected on the Cs and Cgd through the falling edge of Vg (N,j) to achieve linear voltage dropping. Especially, during the reverse discharging process of Cs and Cgd caused by the falling edge of Vg(N,j), delay of time may result. The curves show that the time period when the voltage stays greater than VT is extended. In other words, the thin-film transistor that is supposed to cut off is affected by the parasitic capacitor to maintain conducting. Such an influence is shown as voltage drift of Vd(N,j) at the drain terminal D, which expands the time period when the liquid crystal molecules stay in a rotated state, and what is shown in that the liquid crystal molecules that are supposed not to rotate are now rotated, leading to abnormality of displaying contrast.